In practice, a metal interconnection structure is usually formed by Damascene process in the semiconductor industry, including forming a metal interconnection line on a contact plug, forming an interlayer via on the metal interconnection line and then forming an upper-layer metal interconnection line on the interlayer via. The processes of making the via and lines can be repeated several times to achieve an interconnection of multiple metal layers.
The first metal interconnection line (M1) is implemented by Single Damascene process. Specifically, first, as shown in FIG. 1, on a first dielectric layer 20 and a first metal layer 10 (generally referred to as a contact plug) embedded in the first dielectric layer 20, a first barrier layer 30 and a second dielectric layer 40 are formed (in practice, a barrier layer 12 is sandwiched between the first dielectric layer 20 and the first metal layer 10, which is indicated in the drawings but is not presented in the explanations here for brief). Next, as shown in FIG. 2, the second dielectric layer 40 and the first barrier layer 30 are patterned to form a first trench 50. Subsequently, as shown in FIG. 3, a second barrier layer 32 is formed to cover the second dielectric layer 40 and the bottom and side walls of the first trench 50. Finally, a second metal layer is formed on the second barrier layer 32 to fill the first trench 50.
Currently, the second metal layer is copper. The copper layer may be formed on the second barrier layer 32 as follows. First, as shown in FIG. 4, a first copper layer 42 is formed on the second barrier layer 32. Then, as shown in FIG. 5, a second copper layer 44 is formed on the first copper layer 42 by electrical plating using the first copper layer 42 as plating seed. Finally, as shown in FIG. 6, the second copper layer 44, the first copper layer 42, and the second barrier layer 32 are planarized (by means of chemical mechanical polishing, for example) to expose the second dielectric layer 40.
Further, in the process where copper is used as the filling material for the contact plug, the contact plug may be achieved by means of steps similar to those of the above Single Damascene process. In this case, the first metal layer 10 becomes a metal silicide or a metal gate, and a contact hole is formed by patterning the second dielectric layer 40 and the first barrier layer 30. The remaining metallization steps are kept unchanged.
From the second metal interconnection line (M2), Dual Damascene process is usually adopted in the industrial manufacture to form a metal interconnection line and an underlying via connected thereto at one time. The via is further connected to a lower-layer metal interconnection line. The Dual Damascene process distinguishes from the Single Damascene process in that it adopts two layers of etching resist, two times of exposure and two times of etching so as to form a trench for embedding the metal interconnection line and a through hole in two dielectric layers at one time. The subsequent metallization steps are similar to those of the above described Single Damascene process.
Nowadays, with the continuously decreasing of the device size, interconnection features, including the contact hole, the first trench 50, further trenches (such as the second trench) and the through hole, have a continuously increasing depth-to-width ratio. As a result, it is more and more difficult to fill the features to form a metal interconnection structure satisfying the process requirements. A common problem is that in filling the features with copper to form the interconnects (contact plug, the interlayer via and the metal interconnection lines), voids may be generated in the interconnects, which tend to cause failure of devices.
Generally, taking the case where Single Damascene process is adopted to form a metal interconnection line as an example, one of the reasons why voids may be formed in the metal interconnection line is considered as that: the second barrier layer 32 and the first copper layer 42 (i.e. the seed layer) are formed by means of sputtering to cover the bottom and side walls of the trench and the second dielectric layer 40 in which the trench is embedded, that is, to cover a sharp corner 52 located at the opening of the trench, and portions of the second barrier layer 32 and the first copper layer 42 covering the corner 52 have a thickness greater than portions of the second barrier layer 32 and the first copper layer 42 covering the bottom and side walls and the second dielectric layer 40 in which the trench is embedded. Since the opening of the trench is becoming smaller and smaller in size, the filling of the metal layer at the opening tends to be finished first, resulting in a neck blocking effect, due to which, the further filling of the metal layer into the trench is prevented so that voids are formed in the trench.
Furthermore, with the continuously increasing of the depth-to-width ratio of the trench, it is more and more difficult for the second barrier layer 32 and the first copper layer 42 to be attached to the side walls of the trench. Thus, it is impossible to form a continuous seed layer necessary for the plating. In other words, it is more and more difficult for the second barrier layer 32 and the first copper layer 42 to cover the bottom and side walls of the trench and the second dielectric layer 40 having the trench embedded therein, so that it is impossible to carry out plating of the copper in the lower portion of the trench, resulting in voids or even disconnections.
The above difficulties also occur in the process of forming copper contact plugs and the process of forming metal lines and vias by means of Dual Damascene process. To suppress the occurrence of the voids, those skilled in the art have already made a number of attempts. A basic idea is to reduce the depth-to-width ratio of the contact hole. One way to achieve this is to reduce the thickness of the second barrier layer 32. However, the thickness of the second barrier layer 32 (TaN/Ta, for example) cannot be reduced without limit because the second barrier layer 32 will lose its function if its thickness is reduced to some extent (for example, as to the 22 nm process, the thickness of the second barrier layer 32 generally cannot be less than 6 nm).
Therefore, there is a need for a novel method for forming metal interconnections to suppress the occurrence of voids, which may cause disconnection in a worse case.